After being fabricated, Integrated Circuits (ICs) are tested for proper functional operation and structural integrity using a set of test vectors that contain test inputs and the expected test outputs Test vectors generated by an Automatic Test Pattern Generation (ATPG) software are applied to the chip or device under test (DUT) by an Automatic Test Equipment (ATE). The ICs that successfully passed all the test vectors are qualified as good whereas the ICs that failed on any of the test vectors are qualified as bad or defective. For the defective ICs, the failure information is collected by the ATE and stored in a buffer for further processing using diagnostics tools.
Defects of a defective chip are located using the failure information obtained from the ATE and the test vectors applied to the defective chip as well as the design information with which the chip is fabricated. Diagnostics took, e.g. fault simulation on the failed patterns, are used to identify defective locations. The diagnosis process reports the fault type(s) and the corresponding location(s) that best match the failures observed by the ATE. The matching is typically done using a scoring formula that accounts for the number of predictions mis-predictions and non-predictions. The diagnostics tools are generally useful in identifying yield limners and possibly locating them on the defective IC to help chip designers to find the systematic defects in their designs and to improve them by fixing the cause of such failures.
It is extremely challenging to accurately determine the defect locations in a failing chip due to various reasons. The defect(s) may not behave as modeled faults or there are multiple defect locations in a failing chip. Multiple defects may interact with each other and produce a failing signature that does not match with the faults simulated individually using fault simulator or defect(s) excitation conditions is not met with the values on the neighboring nets. Further, as integrated circuits shrink in size and increase in complexity of design, the probability of having multiple defects in a single integrated circuit (IC) increases.
The diagnosis fault simulation will perform single fault simulation. Thus to determine the possibility of multiple defects, simulating all combinations of faults is impractical. There are some existing methods present to determine the multiple defects.
In one approach for determining multiple defects in an integrated circuit, a time intensive heuristic, e.g. greedy heuristic, for determining the smallest set of faults that explain the maximum number of failures is applied. Existing heuristic based greedy algorithms are often prone to false positives because a single pass is applied to determine the minimum fault set. If the faults during the defect identification process are chosen incorrectly, the final set of fault candidates identified will be incorrect.
Another approach determines multiple defects by back tracing from failing flops, determining the non-overlapping back-cones of logic, and then partitioning the failures. Each partition of failures is assumed to be caused by different sets of defects. The failures are partitioned based on the failing flops whose feeding logic is not overlapping and then perform diagnostics are performed on a separate set of partitioned clusters. This approach may not always lead to successful partition of failures because for overlapping defects, this results in a single cluster of failures. The probability that multiple defects lie physically very near is high and thus their chance of feeding the same failing flops (overlapping logic) is also very high. Therefore, the probability of partitioning the failures caused by multiple defects is not very good. The circuit based fail partitioning doesn't work for compression test modes because in compression test modes the data coming out from scan chains are compressed and getting the list of actual failing flops is very time consuming. Without knowing the list of actual failing flops, the failures cannot be partitioned.
In the above approaches, a single scoring scheme is applied to rank the fault candidates. Faults with inconsistent explanation may get higher rank than the faults with consistent explanation in a different scoring scheme. To illustrate, a fault with an inconsistent explanation is one that does not explain all failures in a failing pattern while a fault with a consistent explanation is one that explains all failures in the failing pattern.
A single scoring formula is applied to determine the score of a fault. This may result in incorrect faults getting higher scores since the scoring formula applied may not be appropriate.
The score is calculated on all the patterns (sequences) simulated. This can result in incorrect faults getting a higher score because an undetected fault is not excited in passing patterns or the failing patterns fail due to random defects. A passing pattern is one where no faults were identified while a failing pattern is one where faults were identified.
The aforementioned approaches are heuristic-based and can produce false positives. A single canned algorithm is applied to determine defect locations. The accuracy of the final results depends on the accuracy of the applied algorithm and alignment of input data to the algorithm. The propagation of error from the defect identification process will cause a significant loss of time during the physical failure analysis and the yield ramp process slows down.
There is therefore a need for a better system or method to minimize the chance of false positives and accurately identify all the multiple defects for all design chips and prioritize or rank the fault locations with their best probability.